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[VHDL-FPGA-Verilog] DDS

Description: 用Verilog编写的DDS逻辑,很好地实现了DDS功能，可以产生各种频率的正弦波。-DDS which was write by Verilog。
Platform: | Size: 443392 | Author: 宋升金 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: Cordic algorithm implementation in verilog for use in DDS
Platform: | Size: 5120 | Author: zcos123 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在MAXPLUSII下开发的基于verilog的直接数字频率合成器-Developed under the MAXPLUSII verilog-based direct digital frequency synthesizer
Platform: | Size: 1926144 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: dds 源代码 verilog 很有意义-dds dds verilog source code makes sense
Platform: | Size: 22528 | Author: changyounghoo | Hits:

[VHDL-FPGA-Verilog] costas

Description: costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Platform: | Size: 6144 | Author: 潇潇 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在ISE环境中，运用verilog语言实现DDS（直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写）的功能-In the ISE environment, use verilog language DDS (direct digital frequency synthesizer (Direct Digital Synthesizer) in abbreviation) of the function
Platform: | Size: 371712 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds的verilog实现 调用dds核 已经实验验证-dds 调用dds核
Platform: | Size: 2048 | Author: 王艳超 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于Verilog HDL的DDS设计与仿真-Verilog HDL-based design and simulation of DDS
Platform: | Size: 313344 | Author: mend | Hits:

[VHDL-FPGA-Verilog] MY-DDS

Description: 利用altera公司的FPGA使用verilog语言实现DDS功能 外加DA 可将数字信号转换成标准正弦信号-Altera FPGA use verilog language of DDS functions plus DA converts digital signals into a standard sine signal
Platform: | Size: 1305600 | Author: 李枫 | Hits:

[VHDL-FPGA-Verilog] DDS-design-based-on-verilog

Description: 用verilog语言设计DDS数字频率合成器-DDS design based on verilog
Platform: | Size: 1049600 | Author: zhxuqin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 使用AD5559,结合quartus中的硬件描述语言,实现了雷达发射信号二相码信号-using AD9959 and combining with verilog to output a rada signal of Binary code
Platform: | Size: 5249024 | Author: chengjingjing | Hits:

[VHDL-FPGA-Verilog] DDS-frequency-synthesizer

Description: 本文主要讨论了Verilog语言的基于DDS的波形发生器的设计。从设计要求入手，本文给出了DDS的详细设计过程，包括各个模块的设计思想，电路图，Verilog语言程序代码。其大致思想为通过频率控制字和相位控制字去控制正弦函数的ROM存储表的地址并对应着得到其幅度值，最终达到输出需要波形的目的。-This paper mainly discusses the design of the Verilog language, the DDS-based waveform generator. Starting from the design requirements, this paper presents the detailed design of the DDS process, including the various modules of the design ideas, schematics, Verilog language code. The general idea of frequency control word and phase control word to control the address of the ROM memory table of the sine function and the corresponding get its amplitude value, and ultimately achieve the purpose of waveform output needs.
Platform: | Size: 814080 | Author: 任健铭 | Hits:

[VHDL-FPGA-Verilog] DDS-SIN

Description: 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
Platform: | Size: 2629632 | Author: 牛倩 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于verilog的DDS设计验证与仿真源代码，在quartus上实现，下载仿真成功-Based on the the the verilog DDS design verification and simulation of the source code, in quartus download simulation success
Platform: | Size: 28672 | Author: baixin358 | Hits:

[Other] dds

Description: 一个用verilog编写的dds发生器，希望能对大家有所帮助 -A set of relatively good the quartus learning Chinese information for beginners, more practical, oh. .
Platform: | Size: 692224 | Author: 李妮 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
Platform: | Size: 3008512 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS-algorithm

Description: 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
Platform: | Size: 1982464 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 直接数字频率合成器dds，用verilog实现，经过quartus验证-Direct digital frequency synthesizer the dds, used verilog achieved after quartus verify
Platform: | Size: 911360 | Author: nilsolov | Hits:

[VHDL-FPGA-Verilog] dds_mul

Description: 简单的多周期dds的verilog编程，出来一个正弦波，可任意改变频率字-Simple multi-cycle dds verilog programming, out of a sine wave, the frequency can be arbitrarily changed words
Platform: | Size: 4069376 | Author: shanshan | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog编写的dds发生器，修改频率字可改频率-dds in verilog
Platform: | Size: 3298304 | Author: wangxiao | Hits:
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